NXP公司的LPC2927/2929是基于ARM968E-S核的微控制器，集成了工作頻率高達125MHz的兩個TCM區塊，全速USB 2.0 OTG和設備控制器，CAN和LIN，56KB SRAM，多達768KB閃存，外接存儲器接口，三個10位ADC以及多個串行和并行接口，可廣泛用于消費類電子，工業，醫療設備和通信市場。本文介紹了LPC2927/2929的主要特性，方框圖，自供電和總線供電設備的LPC2927/2929 USB接口連接圖，USB OTG端口和USB設備端配置以及Hitex 公司的LPC2900 評估板LPC29XX-A1的主要特性和詳細電路圖。
LPC2927/2929 ARM9 microcontroller with CAN, LIN, and USB OTG/Device
The LPC2927/2929 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 OTG and device controller, CAN and LIN, 56 kB SRAM, up to 768 kB flash memory, external memory interface, three 10-bit ADCs, and multiple serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets. To optimize system power consumption, the LPC2927/2929 has a very flexible Clock Generation Unit(CGU) that provides dynamic clock gating and scaling.
LPC2927/2929主要特性：
ARM968E-S processor running at frequencies of up to 125 MHz maximum.
Multi-layer AHB system bus at 125 MHz with four separate layers.
On-chip memory:
Two Tightly Coupled Memories (TCM), 32 kB Instruction TCM (ITCM), 32 kB Data TCM (DTCM).
Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB SRAM.
8 kB ETB SRAM also available for code execution and data.
Up to 768 kB high-speed flash-program memory.
16 kB true EEPROM, byte-erasable and programmable.
Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can be used with the SPI interfaces and the UARTs, as well as for memory-to-memory transfers including the TCM memories.
External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data bus; up to 24-bit address bus.
Serial interfaces:
USB 2.0 full-speed device/OTG controller with dedicated DMA controller and on-chip device PHY.
Two-channel CAN controller supporting Full-CAN and extensive message filtering
Two LINｍａｓｔｅｒcontrollers with full hardware support for LIN communication. The LIN interface can be configured as UART to provide two additional UART interfaces.
Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and RS485(9-bit) support.
Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;Tx FIFO and Rx FIFO.
Two I2C-bus interfaces.
Other peripherals:
One 10-bit ADC with 5.0 V measurement range and eight input channels with conversion times as low as 2.44s per channel.
Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide an additional 16 analog inputs with conversion times as low as 2.44s per channel.Each channel provides a compare function to minimize interrupts.
Multiple trigger-start option for all ADCs: timer, PWM, other ADC, and external signal input.
Four 32-bit timers each containing four capture-and-compare registers linked to I/Os.
Four six-channel PWMs (Pulse-Width Modulators) with capture and trap functionality.
Two dedicated 32-bit timers to schedule and synchronize PWM and ADC.
Quadrature encoder interface that can monitor one external quadrature encoder.
32-bit watchdog with timer change protection, running on safe clock.
Up to 104 general-purpose I/O pins with programmable pull-up, pull-down, or bus keeper.
Vectored Interrupt Controller (VIC) with 16 priority levels.
Up to 21 level-sensitive external interrupt pins, including USB, CAN and LIN wake-up features.
Configurable clock-out pin for driving external system clocks.
Processor wake-up from power-down via external interrupt pins; CAN or LIN activity.
Flexible Reset Generator Unit (RGU) able to control resets of individual modules.
Flexible Clock-Generation Unit (CGU0) able to control clock frequency of individual modules:
On-chip very low-power ring oscillator; fixed frequency of 0.4 MHz; always on to provide a Safe_Clock source for system monitoring.
On-chip crystal oscillator with a recommended operating range from 10 MHz to 25 MHz. PLL input range 10 MHz to 25 MHz.
On-chip PLL allows CPU operation up to a maximum CPU rate of 125 MHz.
Generation of up to 11 base clocks.
Seven fractional dividers.
Second CGU (CGU1) with its own PLL generates USB clocks and a configurable clock output.
Highly configurable system Power Management Unit (PMU):
clock control of individual modules.
allows minimization of system operating power consumption in any configuration.
Standard ARM test and debug interface with real-time in-circuit emulator.
Boundary-scan test supported.
ETM/ETB debug functions with 8 kB of dedicated SRAM also accessible for application code and data storage.
Dual power supply:
CPU operating voltage: 1.8 V5 %.
I/O operating voltage: 2.7 V to 3.6 V; inputs tolerant up to 5.5 V.
144-pin LQFP package.
40℃ to +85℃ ambient operating temperature range.
圖1。LPC2927/2929方框圖
圖2。自供電設備的LPC2927/2929 USB接口
圖3。總線供電設備的LPC2927/2929 USB接口
圖4。LPC2927/2929 USB OTG端口配置
圖5。LPC2927/2929 USB設備端口配置
LPC2900 評估板LPC29XX-A1
This evaluation board hosts the LPC2929 or LPC2939 microcontroller from NXP with an embedded ARM968E-S processor core and with an JTAG interface. In addition the driver chips for the external communication interfaces are included. All microcontroller IO port pins are accessible via connectors. The device drivers can be disabled via jumpers to have control of the microcontroller IO pins.
評估板包括：
Hitex Evaluation Board for ARM with NXP ARM9 microcontroller LPC2929 or
Hitex Evaluation Board for ARM with NXP ARM9 microcontroller LPC2939
support for internal 768kByte FLASH and 80kByte SRAM
support of 2 CAN and 2 RS232 ports
external SRAM 512k x 8 (limitation for evaluation board V1.0)
2 x small 7-segment LEDs attached to port pins
3 buttons for reset, IRQ and port pin
32,768kHz + 16MHz Quartz
configuration of ports, reset, etc. via jumpers
JTAG debugger support with JTAG connector
2 x 24 pin connector for BLDC motor add-on board
1.8V and 3.3V power regulator,+5V directly from USB
USB device support
USB-OTG device support (LPC2939 only)
USB powered or alternative external power via BNC connector
